Dummy Register 1; Base Address Register - Motorola MVME172 Programmer's Reference Manual

Dummy Register 1

Dummy Register 1 is hard-wired to all zeros. Writes to this register are
ignored; however, the MCECC always terminates the cycles properly with
TA*.
ADR/SIZ
BIT 31
NAME
0
OPER
R
RESET X

Base Address Register

These eight bits are combined with the two most significant bits in Register
7 (the next register) to form BAD31-BAD22, which defines the base
address of the memory. For larger memory sizes, the lower significant bits
are ignored.
The bit assignments for the Base Address Register are:
ADR/SIZ
BIT 31
NAME
BAD31
OPER
R/W
RESET 0 PLS
http://www.mcg.mot.com/literature
Difference from MEMC040: register = Alternate Control
for MEMC040; register = $00 for MCECC.
1st $FFF43010/2nd $FFF43110 (8-bits)
30 29
0 0
R R
X X
Difference from MEMC040: none.
1st $FFF43014/2nd $FFF43114 (8-bits)
30 29 28
BAD30 BAD29 BAD28
R/W R/W R/W
0 PLS 0 PLS 0 PLS
28 27 26
0 0 0
R R R
X X X
27 26
BAD27 BAD26
R/W R/W
0 PLS 0 PLS
Programming Model
25 24
0 0
R R
X X
25 24
BAD25 BAD24
R/W R/W
0 PLS 0 PLS
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