Error Syndrome Register; Defaults Register 2 - Motorola MVME172 Programmer's Reference Manual

MCECC

Error Syndrome Register

ADR/SIZ
BIT
NAME
OPER
RESET
5
Defaults Register 1
ADR/SIZ
BIT
NAME
OPER
RESET
5-34
1st $FFF43070/2nd $FFF43170 (16-bits)
31 30 29
S7 S6 S5
R R R
0 PLS 0 PLS 0 PLS
S7-S0 SYNDROME7-0 reflects the syndrome value at the last
logging of an error. The eight bit code indicates the
position of the data error. When all the bits are zero, there
is no error. Note that if the logged error was non-
correctable, then these bits are meaningless. Refer to the
section on Syndrome Decode.
1st $FFF43074/2nd $FFF43174 (8-bits)
31 30
WRHDIS STATCOL
R/W R/W
0 PL V PLS
It is not recommended that non-test software write to this register.
RSIZ2-RSIZ0
RSIZ2-RSIZ0 determine the size of the DRAM array that
is assumed by the MCECC. They control the size as
follows:
28 27
S4 S3
R R
0 PLS 0 PLS
29 28 27
FSTRD SELI1 SELI0 RSIZ2 RSIZ1 RSIZ0
R/W R/W R/W
V PLS V PLS V PLS V PLS V PLS V PLS
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26 25 24
S2 S1 S0
R R R
0 PLS 0 PLS 0 PLS
26 25 24
R/W R/W R/W