Table 4-1. Ip2 Chip Clock Cycles - Motorola MVME172 Programmer's Reference Manual

IP2 Chip
MC68060
4
25 MHz
32 MHz
32 MHz
4-6

Table 4-1. IP2 Chip Clock Cycles

Bus Frequency
IP
8 MHz
8 MHz
32 MHz
(Note 5)
Notes 1. This column is a measure of IndustryPack bandwidth for
back to back cycles for a local bus master which is accessing
a memory or I/O space location on an IndustryPack. It
assumes a zero wait state acknowledge reply from the
IndustryPack.
2. This column is a measure of IndustryPack bandwidth for
DMA burst cycles between a local bus slave and a memory
or I/O space location on an IndustryPack. It assumes a zero
wait state acknowledge reply from the IndustryPack.
3. This column is a measure of IndustryPack bandwidth for
DMA single cycles between a local bus slave and a memory
or I/O space location on an IndustryPack. It assumes a zero
wait state acknowledge reply from the IndustryPack.
4. Burst mode sDMA is not supported when both bus
frequencies are 32 MHz.
5. Because the specified band width assumes a zero wait state
IndustryPack cycle, it would be difficult to achieve the stated
bandwidths for an IP bus frequency of 32 MHz.
Period and Bandwidth to 32-Bit IP Space
Back to Back Four Cycle
Examine DMA Burst
(Note 1) (Note 2)
4 IP clocks 10 IP clocks
8 MB/sec 12.8 MB/sec
3 IP clocks 10 IP clocks
10.6 MB/sec 12.8 MB/sec
6 IP clocks 12 IP clocks
21 MB/sec 42 MB/sec
(Note 4)
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Single Cycle
DMA
(Note 3)
4 IP clocks
8 MB/sec
4 IP clocks
8 MB/sec
6 IP clocks
21 MB/sec