Interrupt Level Register 2 (Bits 0-7); Interrupt Level Register 3 (Bits 24-31) - Motorola MVME172 Programmer's Reference Manual

VMEchip2

Interrupt Level Register 2 (bits 0-7)

2
ADR/SIZ
BIT
NAME
OPER
RESET

Interrupt Level Register 3 (bits 24-31)

ADR/SIZ
BIT
NAME
OPER
RESET
2-92
$FFF4007C (8 bits [6 used] of 32)
7 6
LM1 LEVEL
R/W
0 PSL
This register is used to define the level of the GCSR LM0 interrupt and the
GCSR LM1 interrupt.
LM0 LEVEL These bits define the level of the GCSR LM0 interrupt.
LM1 LEVEL These bits define the level of the GCSR LM1 interrupt.
$FFF40080 (8 bits [6 used] of 32)
31 30 29
SW7 LEVEL
R/W
0 PSL
This register is used to define the level of the software 6 interrupt and the
software 7 interrupt.
SW6 LEVEL These bits define the level of the software 6 interrupt.
SW7 LEVEL These bits define the level of the software 7 interrupt.
5 4 3
28 27
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2 1 0
LM0 LEVEL
R/W
0 PSL
26 25 24
SW6 LEVEL
R/W
0 PSL