DMAC Byte Counter
ADR/SIZ
BIT
31
NAME
OPER
RESET
In the direct mode, this counter is programmed with the number of bytes
of data to be transferred.
Table Address Counter
ADR/SIZ
BIT
31
NAME
OPER
RESET
In the command chaining mode, this counter should be loaded by the
processor with the starting address of the list of commands. This register
gets reloaded by the DMAC with the starting address of the current
command. The last command in a list should have bits 0 and 1 set in the
next command pointer.
VMEbus Interrupter Control Register
ADR/SIZ
BIT
31
NAME
OPER
RESET
http://www.mcg.mot.com/literature
$FFF40040 (32 bits)
DMAC Byte Counter
$FFF40044 (32 bits)
Table Address Counter
$FFF40048 (8 bits [7 used] of 32)
30
29
28
IRQ1S
IRQC
R/W
S
0 PS
0 PS
LCSR Programming Model
. . .
R/W
0 PS
. . .
R/W
0 PS
27
26
IRQS
R
0 PS
0
0
25
24
IRQL
S
0 PS
2-61
2