Lanc Bus Error Interrupt Control Register - Motorola MVME172 Programmer's Reference Manual

MC2 Chip

LANC Bus Error Interrupt Control Register

ADR/SIZ
3
BIT
NAME
OPER
RESET
3-32
7 6 5
SC1 SC0 INT
R/W R/W R
0 PL 0 PL 0 PL
IL2-IL0 Interrupt Request Level. These three bits select the
interrupt level for the 82596CA LANC bus error
condition. Level 0 does not generate an interrupt.
ICLR Writing a logic 1 into this bit clears the INT status bit.
This bit is always read as zero.
IEN Interrupt Enable. When this bit set high, the interrupt is
enabled. The interrupt is disabled when this bit is low.
INT Interrupt Status. When this bit is high, a LANC Bus Error
interrupt is being generated at the level programmed in
IL2-IL0.
SC0 Snoop Control.
0 Snoop enabled
1 Snoop disabled
$FFF42028 (8 bits)
4 3
IEN ICLR
R/W C R/W
0 PL 0 0 PL
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2 1 0
IL2 IL1 IL0
R/W R/W
0 PL 0 PL