I/O Control Register 1 - Motorola MVME172 Programmer's Reference Manual

I/O Control Register 1

ADR/SIZ
BIT
23
NAME MIEN
OPER R/W
RESET
0 PSL
This register is a general purpose I/O control register. Bits 16-19 control
the direction of the four General Purpose I/O pins (GPIO0-3).
GPOEN0
GPOEN1
GPOEN2
GPOEN3
ABRTL
ACFL
SYSFL
MIEN
http://www.mcg.mot.com/literature
$FFF40088 (8 bits of 32)
22 21 20
SYSFL ACFL ABRTL
R R R
X X X
When this bit is low, the GPIO0 pin is an input.
When this bit is high, the BPIO0 pin is an output.
When this bit is low, the GPIO1 pin is an input.
When this bit is high, the BPIO1 pin is an output.
When this bit is low, the GPIO2 pin is an input.
When this bit is high, the BPIO2 pin is an output.
When this bit is low, the GPIO3 pin is an input.
When this bit is high, the BPIO3 pin is an output.
This bit indicates the status of the
When this bit is high, the
When this bit is low, the
This bit indicates the status of the ACFAIL signal line on
the VMEbus. When this bit is high, the ACFAIL signal
line is active. When this bit is low, the ACFAIL signal line
is not active.
This bit indicates the status of the SYSFAIL signal line on
the VMEbus. When this bit is high, the SYSFAIL signal
line is active. When this bit is low, the SYSFAIL signal
line is not active.
When this bit is low, all interrupts controlled by the
VMEchip2 are masked. When this bit is high, all
interrupts controlled by the VMEchip2 are not masked.
LCSR Programming Model
19 18 17
GPOEN3 GPOEN2 GPOEN1 GPOEN0
R/W R/W R/W
0 PS 0 PS 0 PS
switch.
ABORT
switch is depressed.
ABORT
switch is not depressed.
ABORT
2
16
R/W
0 PS
2-97