Interrupt Level Register 4 (Bits 0-7); Vector Base Register - Motorola MVME172 Programmer's Reference Manual

VMEchip2

Interrupt Level Register 4 (bits 0-7)

2
ADR/SIZ
BIT
NAME
OPER
RESET

Vector Base Register

ADR/SIZ
BIT
NAME
OPER
RESET
2-96
$FFF40084 (8 bits [6 used] of 32)
7 6
VIRQ2
R/W
0 PSL
This register is used to define the level of the VMEbus IRQ1 interrupt and
the VMEbus IRQ2 interrupt. The VMEbus level 1 (IRQ1) interrupt and the
VMEbus level 2 (IRQ2) interrupt may be mapped to any local bus interrupt
level.
VIRQ1 LEVEL These bits define the level of the VMEbus IRQ1 interrupt.
VIRQ2 LEVEL These bits define the level of the VMEbus IRQ2 interrupt.
31 30 29
VBR 0
R/W
0 PSL
This register is used to define the interrupt base vectors.
VBR 1 These bits define the interrupt base vector 1.
VBR 0 These bits define the interrupt base vector 0.
Note
Refer to Table 2-3, Local Bus Interrupter Summary, for
further information.
A suggested setting for the Vector Base Register for the
VMEchip2 is: VBR0 = 6, VBR1 = 7 (i.e., setting the Vector
Base Register at address $FFF40088 to $67xxxxxx). This
produces a Vector Base0 of $60 corresponding to the "X" in
Table 2-3, and a Vector Base1 of $70 corresponding to the
"Y" in Table 2-3.
5 4 3
$FFF40088 (8 bits of 32)
28 27
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2 1 0
VIRQ1 LEVEL
R/W
0 PSL
26
25 24
VBR 1
R/W
0 PSL