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DMA Enable Function
There are certain DMA channel contexts which are illegal. If an attempt is
made to program the DMA control register 1 for each channel a and b or c
and d to an illegal state, the DEN (DMA enable control bit) will not set
when it is loaded to a one via a processor store instruction. This condition
can be tested by writing the DEN bit to a one and reading a zero. Refer to
the description of the DMA Enable Register for the required programming
sequence of the control registers and enable bits.
The following are legal contexts for DMA channel configurations. Note
that configuration rules for DMA controllers for IP_a and IP_b are defined.
The same relationships exist for IP_c and IP_d.
DMA Control and Status Register Set Definition
The four sets of DMA controller CSRs are almost identical in
functionality. Each register set is grouped as DMACa, DMACb, DMACc,
and DMACd. These register sets are shown pictorially in the CSR register
summary section. Only one register set is defined except that the offset is
noted for the four possible values. Refer to the definitions of bit 1 of the
DMA Control Register 1 for a description of how the register sets are
associated with the physical DMA request from the Industry Packs.
The registers which control IP_c and IP_d are not used on the 200/300-
Series MVME172.
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If IP_a data bus is 8 or 16 bits, there are not any restrictions placed
on IP_b.
If IP_a data bus is 32 bits and the ADMA mode is selected, then the
DMA controller associated with IP_b cannot be used.
If A_CH1 bit is set in the DMA controller register associated with
IP_b and both channel A and B operate in the SDMA mode, then the
DMA channels associated with IP_a and IP_b can both be used if
the data width for channel A and B are set equal. This case allows
the DMA channel that normally re- sponds to IP_b-DMAreq_0 pin
to respond to IP_a-DMAreq_1 pin. This enables full duplex
communications operation at IP_a.
Programming Model
4-33
4
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