Table 3-5. Dram Size Control Bit Encoding; Table 3-6. Sram Size Control Bit Encoding - Motorola MVME172 Programmer's Reference Manual

MC2 Chip
3
3-28

Table 3-5. DRAM Size Control Bit Encoding

DZ2 - DZ0 DRAM Configuration
$0 Not defined for MVME172
$1 Not defined for MVME172
$2 Not defined for MVME172
$3 Not defined for MVME172
$4 4 MByte (non-interleaved)
$5 8 MByte (non-interleaved)
$6 DRAM is not present
$7 16 MByte (interleaved)
SZ1 - SZ0 are initialized at reset to a value which is
determined by the contents of a factory-programmed
resident device

Table 3-6. SRAM Size Control Bit Encoding

SZ1 - SZ0
$0
$1
$2
$3
F0 F0 set to a 0 indicates that one 28F016SA 2M x 8 Flash
memory device is used. F0 set to a 1 indicates that four
28F020 256K x 8 Flash memory devices are used.
SRAM Configuration
128 KB
512 KB
1 MB
2 MB
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