Table 1-11. Mcecc Internal Register Memory Map - Motorola MVME172 Programmer's Reference Manual

Table 1-10. IP2 Chip Memory Map - Control and Status Registers
Register Register
Offset Name
$80 PACER INT
CONTROL
$81 PACER GEN PLTY
CONTROL
$82 PACER T15
TIMER
$83 PACER
TIMER
The following MCECC memory map applies only to the 200/300-Series MVME172
boards.

Table 1-11. MCECC Internal Register Memory Map

MCECC Base Address = $FFF43000 (1st); $FFF43100 (2nd)
Register Register
Offset Name
$00 CHIP ID
$04 CHIP REVISION
$08 MEM CONFIG
$0C DUMMY 0
$10 DUMMY 1
$14 BASE ADDRESS
$18 DRAM CONTRL
$1C BCLK FREQ
$20 DATA CONTRL
$24
SCRUB CNTRL
$28 SCRUB PERIOD
$2C SCRUB PERIOD
$30 CHIP PRESCALE
$34 SCRUB TIME ON/OFF
$38 SCRUB PRESCALE
$3C SCRUB PRESCALE
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(Continued)
D7 D6 D5
0 IRE INT
PLS 0
T14 T13
T7 T6 T5
D31 D30 D29
CID7 CID6 CID5
REV7 REV6 REV5
FSTRD
0 0 0
0 0 0
BAD31 BAD30 BAD29
BAD23 BAD22 RWB5
BCK7 BCK6 BCK5
0 0 DERC
RACODE RADATA HITDIS
SBPD15 4
SBPD1 SBPD1
7 6
SBPD SBPD SBPD
CPS7 CPS6 CPS5
SRDIS 0 STON2
0 0 SPS21
15 14
SPS SPS SPS
Register Bit Names
D4 D3
IEN ICLR
EN CLR PS2
T12 T11 T10
T4 T3
Register Bit Names
D28 D27
CID4 CID3 CID2
REV4 REV3 REV2
1 0 MSIZ2
0 0 0
0 0 0
BAD28 BAD27 BAD26
SWAIT RWB3 NCEIEN
BCK4 BCK3 BCK2
ZFILL RWCKB 0
SCRB SCRBEN 0
3 2 1
SBPD1 SBPD1 SBPD1
5 4 3
SBPD SBPD SBPD
CPS4 CPS3 CPS2
1 0 STOFF2
STON STON
0 19
SPS2 SPS SPS
13 12 11
SPS SPS SPS
Memory Maps
D2 D1 D0
IL2 IL1 IL0
PS1 PS0
T9 T8
T2 T1 T0
D26 D25 D24
CID1 CID0
REV1 REV0
MSIZ1 MSIZ0
0 0
0 0
BAD25 BAD24
NCEBEN RAMEN
BCK1 BCK0
0 0
SBEIEN IDIS
0 9 8
SBPD SBPD
2 1 0
SBPD SBPD
CPS1 CPS0
1 0
STOFF STOFF
18 17 16
SPS SPS
10 9 8
SPS SPS
1-35
1