Table 5-1. Mcecc Specifications; Cache Coherency - Motorola MVME172 Programmer's Reference Manual

Random, non-burst writes are the slowest kind of access because they
require that the MCECC pair perform a read-modify-write cycle to the
DRAM in order to complete. The MCECC pair responds to the local bus
in two clocks during random writes, but then it takes another eight clocks
for the DRAM read-modify-write cycle to complete, thereby making the
effective cycle time 10 clocks if the following access by the local bus
master is to DRAM. This boils down to two clocks for one random write,
and 10 clocks for sustained random writes.
The performance specifications for the MCECC are shown in
Descriptions
Reads, BERR off, FSTRD = 1
Reads, FSTRD = 0
Reads, BERR on
Writes

Cache Coherency

The MCECC pair supports the MC68060 caching scheme on the local bus
by always providing 32 bits of valid data during DRAM read cycles
regardless of the number of bytes requested by the local bus master for the
cycle. It also supports cache coherency by monitoring the snoop control
signal lines on the local bus and behaving appropriately based on their
value.
When the snoop control signal lines (SC1, SC0) indicate that snooping is
inhibited, the MCECC pair ignores the memory inhibit (MI*) signal line.
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Table 5-1. MCECC Specifications

Specifications
4 clock cycles for random reads
4-1-1-1 clock cycles for burst reads (sustained)
5 clock cycles for random reads
5-1-1-1 clock cycles for burst reads (sustained)
5 clock cycles for random reads
5-1-1-1 clock cycles for burst reads (sustained)
2 to 10 clock cycles for random non-burst writes
2-1-1-1 clock cycles for burst writes (sustained)
Functional Description
Table 5-1.
5-3
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