Watchdog Timer Control Register - Motorola MVME172 Programmer's Reference Manual

Watchdog Timer Control Register

The watchdog timer control logic in the MC2 chip is used with the "No
VMEbus Interface" option. This function is duplicated at the same bit
locations in the VMEchip2 at location $FFF40060. The VMEchip2 has the
additional option of selecting SYSRESET (i.e., VMEbus reset). It is
permissible to enable the watchdog timer in both the VMEchip2 and the
MC2 chip.
ADR/SIZ
BIT 23
NAME
OPER
R
RESET 0
WDEN
WDRSE
WDBFE
WDTO
WDCC
WDCS
http://www.mcg.mot.com/literature
$FFF42044 (8 bits)
22 21 20
WDCS WDCC WDTO
C C R
0 P 0 P 0 P
When this bit is high, the watchdog timer is enabled.
When this bit is low, the watchdog timer is not enabled.
When this bit is high, and a watchdog time-out occurs, a
LRESET is generated. When this bit is low, a watchdog
time-out does not cause a reset.
When this bit is high and the watchdog timer has timed
out, the MC2 chip asserts the BRDFAIL signal pin. When
this bit is low, the watchdog timer does not contribute to
the BRDFAIL signal on the MC2 chip.
When this status bit is high, a watchdog time-out has
occurred. When this status bit is low, a watchdog time-out
has not occurred. This bit is cleared by writing a one to the
WDCS bit in this register.
When this bit is set high, the watchdog counter is reset.
The counter must be reset within the time-out period or a
watchdog time-out occurs.
When this bit is set high, the watchdog time-out status bit
(WDTO bit in this register) is cleared.
Programming Model
19 18 17
WDBFE WDRSE
R/W R R/W
0 PL 0 0 PL
3
16
WDEN
R/W
0 PL
3-43