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IP2 Chip
IP RESET Register
ADR/SIZ
BIT
NAME
4
OPER
RESET
4-30
7
6
0
0
R
R
0 R
0 R
0 R
RES
Setting RES to a one asserts the IP2 chip IPRESET*
signal. IPRESET* is intended to be connected to the
Reset* signal on all four IndustryPacks. When software
sets the RES bit, IPRESET* stays asserted until software
clears RES.
Note
The MVME172 does not comply with the IP specification
regarding reset. The MVME172 does not monitor Vcc and
assert reset if Vcc is below a certain threshold. The IPRESET
signal to the IP bus is asserted when the there is a cold power
up reset. This reset will be asserted until the power supplies
are stable.
$FFFBC01F (8 bits)
5
4
3
0
0
0
R
R
R
0 R
0 R
Computer Group Literature Center Web Site
2
1
0
0
0
RES
R
R
R
0 R
0 R
0 R
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