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Scrub Control Register
ADR/SIZ
BIT
31
NAME
RACODE RADATA
OPER
R/W
RESET
V PLS
IDIS
SBEIEN
SCRBEN This control bit enables the scrubber to operate. When
SCRB
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1st $FFF43024/2nd $FFF43124 (8-bits)
30
29
28
HITDIS
SCRB SCRBEN 0
R/W
R/W
R
0 PLS
V PLS
0 PLS 0 PLS
When cleared, the Image DISable bit allows writes to the
upper MCECC control registers to duplicate the data to
the lower MCECC control registers. When IDIS is set, the
lower MCECC control registers are written separately by
the data on D00-D16. IDIS should only be set for test
purposes.
Setting SBEIEN causes the logging of a single bit error to
create a true pulse on the INT signal pin.
SCRBEN is set, the MCECC immediately performs a
scrub of the entire DRAM array. When the scrub is
complete, if software has cleared SCRBEN, then
scrubbing is not done again, until software sets the
SCRBEN bit. If software has not cleared the SCRBEN bit,
then when the amount of time indicated in the Scrub
Period (SBPD) Register expires, the MCECC scrubs the
DRAM array again. It continues to perform scrubs of the
entire DRAM array at the frequency indicated in the
SBPD Register. The scrubber does not start a new scrub
once the SCRBEN bit is cleared. The time between scrubs
is approximately two seconds times the value stored in the
SBPD Register. Note that power-up, local, or software
reset stops the scrubber.
This status bit reflects the state of the scrubber. When the
scrubber is in the process of doing a scrub, this bit is set.
When the scrubber is between scrubs, this bit is cleared.
Programming Model
27
26
25
SBEIEN
R/W
R
R/W
X
0 PLS
24
IDIS
R/W
0 PLS
5
5-23
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