Mvme172 Version Register - Motorola MVME172 Programmer's Reference Manual

MVME172 Version Register

The contents of a PAL and the state of an 8-position jumper block are
translated to bit settings of the General Purpose Inputs Register, Version
Register and DRAM/SRAM Options Register when the MC2 chip is reset.
These registers are read only. Writes to these registers are terminated
without exception but do not change their contents.
ADR/SIZ
BIT 15
NAME
V7
OPER
R
RESET
V0
V1
V2
http://www.mcg.mot.com/literature
$FFF4202C (8 bits)
14 - 9
V6 - V1
R
Application Specific
V0 and V4 indicated the speed of the processor and local
bus. Refer to the following table for the bit definitions.
V0 V4
Processor Type
0 MC68LC060
0 MC68060
1 0 MC68LC060
1 1 MC68060
** No plans to productize this combination.
V1 set to a one indicates that the VMEchip2 ASIC is not
present. V1 set to a zero indicates that a VMEbus interface
is present.
If V1 = 0, the MC2 chip reset logic and local bus access
timer are inhibited.
V2 set to a one indicates that the SCSI interface is not
present. V2 set to a zero indicates that a SCSI interface is
present.
Programming Model
8
V0
R
Processor/Bus
Frequency
50/25 **
50/25 **
64/32
60/30
3-35
3