Digital Trunk Clocking - NEC Electra Elite IPK II System User Manual

Electra Elite IPK II
Enhancements
This feature was added to the documentation with Version 2000. This feature is available with
version 1000 or higher.
Description
The IPK II CPUII has a built-in clock source for all digital trunk cards. Digital trunk cards are connected
via an internal PLO (Phase Locked Oscillator) to derive Primary Clock from the network in priority order.
If priority is set up incorrectly, or if two primary clocks are coming in, slips may occur causing improper
data synchronization. The Phase Locked Oscillator (PLO) equipped with the IPK II CPUII ETU is the
timing source for all digital trunk ETUs in the system. The PLO synchronizes the system and clock
signals from another office. When the IPK II is a clock receiver office, the PLO generates the clock
signal according to the source clock signals received from the source office in the network. The source
clock signals are extracted from digital trunk ETUs and supplied to the PLO.
The PLO synchronization source priorities are as follows:
1. PRI
2. DTI (External)
3. BRI
4. CPU
Conditions
If multiple PRIs exist, the system chooses the first one that synchronizes with the carrier.

If there are multiple PRIs, and the one being used for the source goes down, the system

begins to count forward in slot numbers looking for the next available PRI.
If multiple BRIs exist and no PRI or DTI (External) exists, the IPK II CPU chooses the first

BRI that synchronized with the carrier.
If there is one PRI, and the one being used for the source goes down, the IPK II CPU looks

to see if any BRIs are installed in the system. If there are no BRIs, the IPK II CPU becomes
the new synchronization source. The reason for this is when a PRI is installed in the
system, all T1s must be assigned as (INTERNAL). T1 (INTERNAL) is not a clocking
priority.

Digital Trunk Clocking

Digital Trunk Clocking
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