Table of Contents
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Instruc- Mnemonic
tion
Group
Uncon- BR
ditional
Branch
Condi-
BC
tional
BNC
Branch BZ
BNZ
BT
BF
BTCLR
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Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
2. Clock indicates when a program is in the internal ROM area.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
514
CHAPTER 23 INSTRUCTION SET
Operands
Byte
!addr16
3
12
$addr16
2
12
AX
2
16
$addr16
2
12
$addr16
2
12
$addr16
2
12
$addr16
2
12
saddr.bit, $addr16
3
16
sfr.bit, $addr16
4
—
A.bit, $addr16
3
16
PSW.bit, $addr16
3
—
[HL].bit, $addr16
3
20
saddr.bit, $addr16
4
20
sfr.bit, $addr16
4
—
A.bit, $addr16
3
16
PSW.bit, $addr16
4
—
[HL].bit, $addr16
3
20
saddr.bit, $addr16
4
20
sfr.bit, $addr16
4
—
A.bit, $addr16
3
16
PSW.bit, $addr16
4
—
[HL].bit, $addr16
3
20
Clock
Note 1
Note 2
PC ← addr16
—
PC ← PC + 2 + jdisp8
—
← A, PC
—
PC
H
PC ← PC + 2 + jdisp8 if CY = 1
—
PC ← PC + 2 + jdisp8 if CY = 0
—
PC ← PC + 2 + jdisp8 if Z = 1
—
PC ← PC + 2 + jdisp8 if Z = 0
—
PC ← PC + 3 + jdisp8
18
if (saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
22
PC ← PC + 3 + jdisp8 if A.bit = 1
—
PC ← PC + 3 + jdisp8 if PSW.bit = 1
18
PC ← PC + 3 + jdisp8 if (HL).bit = 1
22 + 2n
PC ← PC + 4 + jdisp8
22
if (saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
22
PC ← PC + 3 + jdisp8 if A.bit = 0
—
PC ← PC + 4 + jdisp8 if PSW.bit = 0
22
PC ← PC + 3 + jdisp8 if (HL).bit = 0
22 + 2n
PC ← PC + 4 + jdisp8
24
if (saddr.bit) = 1
then reset (saddr.bit)
PC ← PC + 4 + jdisp8 if sfr.bit = 1
24
then reset sfr.bit
PC ← PC + 3 + jdisp8 if A.bit = 1
—
then reset A.bit
PC ← PC+4 + jdisp8 if PSW.bit = 1 ×
24
then reset PSW.bit
24 + 2n +2m PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
CPU
Operation
Z AC CY
← X
L
) selected by processor clock control
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