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FRC
XT1/P04
Subsystem
f
XT
clock oscillator
circuit
XT2
X1
Main system
f
X
clock oscil-
lator circuit
X2
STOP
Figure 7-1. Clock Generator Block Diagram
Prescaler
f
f
f
f
X
X
X
X
2
2
2
2
3
2
4
MCC
FRC
CLS
CSS
PCC2
Processor clock control register
Internal bus
Watch timer, clock output function
Prescaler
Standby
Wait
control
control
circuit
circuit
To INTP0
sampling
clock
3
PCC1 PCC0
Clock to peripheral hardware
CPU clock
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