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Instruc- Mnemonic
tion
Group
Bit
AND1
Manipu-
lation
OR1
XOR1
SET1
CLR1
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SET1
CLR1
NOT1
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
2. Clock indicates when a program is in the internal ROM area.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
512
CHAPTER 23 INSTRUCTION SET
Operands
Byte
CY, saddr.bit
3
12
CY, sfr.bit
3
—
CY, A.bit
2
8
CY, PSW.bit
3
—
CY, [HL].bit
2
12
CY, saddr.bit
3
12
CY, sfr.bit
3
—
CY, A.bit
2
8
CY, PSW.bit
3
—
CY, [HL].bit
2
12
CY, saddr.bit
3
12
CY, sfr.bit
3
—
CY, A.bit
2
8
CY, PSW.bit
3
—
CY, [HL].bit
2
12
saddr.bit
2
8
sfr.bit
3
—
A.bit
2
8
PSW.bit
2
—
[HL].bit
2
12
saddr.bit
2
8
sfr.bit
3
—
A.bit
2
8
PSW.bit
2
—
[HL].bit
2
12
CY
1
4
CY
1
4
CY
1
4
Clock
Note 1
Note 2
CY ← CY∧ (saddr.bit)
14
CY ← CY∧ sfr.bit
14
CY ← CY∧ A.bit
—
CY ← CY∧ PSW.bit
14
CY ← CY∧ (HL).bit
14 + 2n
CY ← CY∨ (saddr.bit)
14
CY ← CY∨ sfr.bit
14
CY ← CY∨ A.bit
—
CY ← CY∨ PSW.bit
14
CY ← CY∨ (HL).bit
14 + 2n
CY ← CY ∨ (saddr.bit)
14
CY ← CY ∨ sfr.bit
14
CY ← CY ∨ A.bit
—
CY ← CY ∨ PSW.bit
14
CY ← CY ∨ (HL).bit
14 + 2n
(saddr.bit) ← 1
12
sfr.bit ← 1
16
A.bit ← 1
—
PSW.bit ← 1
12
(HL).bit ← 1
16 + 2n + 2m
(saddr.bit) ← 0
12
sfr.bit ← 0
16
A.bit ← 0
—
PSW.bit ← 0
12
(HL).bit ← 0
16 + 2n + 2m
CY ← 1
—
CY ← 0
—
CY ← CY
—
CPU
Operation
Z AC CY
×
×
) selected by processor clock control
Flag
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
0
×
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