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(b) Address
(c) Transfer direction specification
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
The 7 bits following the start condition signal are defined as an address.
The 7-bit address data is output by the master device to specify a specific slave from among those connected
to the bus line. Each slave device on the bus line must therefore have a different address.
Therefore, after a slave device detects the start condition, it compares the 7-bit address data received and
the data of the slave address register (SVA). After the comparison, only the slave device in which the data
are a match becomes the communication partner, and subsequently performs communication with the
master device until the master device sends a start condition or stop condition signal.
SCL
SDA0 (SDA1)
The 1-bit data that follows the 7-bit address data will be sent from the master device, and it is defined as
the transfer direction specification bit.
If this bit is 0, it is the master device which will send data to the slave. If it is 1, it is the slave device which
will send data to the master.
Figure 16-40. Transfer Direction Specification
SCL
SDA0 (SDA1)
Figure 16-39. Address
1
2
3
4
A6
A5
A4
Address
1
2
3
4
A6
A5
A4
A3
5
6
7
A3
A2
A1
A0
5
6
7
8
A2
A1
A0
R/W
Transfer direction
specification
R/W
381
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