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(3) Slave wait release (slave reception)
Slave wait release operation is performed by WREL flag (bit 2 of interrupt timing specification register (SINT))
setting or execution of a serial I/O shift register 0 (SIO0) write instruction.
When the slave receives a data, if the SCL line will immediately become high-impedance state by executing of
write instruction to the SIO0, 1st bit data from the master may not be received. This is because if SCL line is
being high-impedance state during execution of write instruction to the SIO0 (until next instruction execution),
SIO0 does not start the operation. Therefore receive the data by manipulating the P27 output latch using program
as shown in the Figure 16-49.
For these timings, see Figure 16-45.
Master device operation
Software operation
Hardware operation
Transfer line
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SCL
SDA0 (SDA1)
Slave device operation
Software operation
Hardware operation
402
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
Figure 16-49. Slave Wait Release (Reception)
Setting
ACKD
9
A0
W
ACK
ACK
output
Writing
FFH
to SIO0
Setting
CSIIF0
D7
P27
Write
output
FFH
latch 0
to SIO0
Setting
Wait
CSIIF0
release
Serial transmission
1
2
3
D6
D5
P27
output
latch 1
Serial reception
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