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CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries)
(2) Communication operation
The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception
is carried out bit-wise in synchronization with the serial clock.
Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of
the serial clock (SCK0).
The transmit data is held in the SO0 latch and is output from the SB0/P25 (or SB1/P26) pin with MSB set at start.
The receive data input from the SB0 (or SB1) pin is latched into the SIO0 at the rising edge of SCK0.
Upon termination of 8-bit transfer, the SIO0 operation stops automatically and the interrupt request flag (CSIIF0)
is set.
Figure 15-33. 2-Wire Serial I/O Mode Timings
1
2
3
4
5
6
7
8
SCK0
SB0 (SB1)
D7
D6
D5
D4
D3
D2
D1
D0
CSIIF0
End of Transfer
Transfer Start at the falling edge of SCK0
The SB0 (or SB1) pin specified for the serial data bus serves for N-ch open-drain input/output and thus it must
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be externally pulled up. Because it is necessary to be set to high-impedance the N-ch open-drain output for data
reception, write FFH to SIO0 in advance.
The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be
manipulated by setting bit 0 (RELT) or bit 1 (CMDT) of the serial bus interface control register (SBIC).
However, do not carry out this manipulation during serial transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output
latch (refer to 15.4.5 SCK0/P27 pin output manipulation).
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