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(1) Serial I/O shift register 0 (SIO0)
This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift
operation) in synchronization with the serial clock.
SIO0 is set with an 8-bit memory manipulation instruction.
When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.
In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1).
In reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0.
The SBI mode, 2-wire serial I/O mode, and I
input and output. Thus, in the case of a device for reception, write FFH to SIO0 in advance (except when address
reception is carried out by setting bit 5 (WUP) of CSIM0 to 1).
In the SBI mode, the busy state can be cleared by writing data to SIO0. In this case, bit 7 (BSYE) of the serial
bus interface control register (SBIC) is not cleared to 0.
RESET input makes SIO0 undefined.
Caution
(2) Slave address register (SVA)
This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus.
SVA is set with an 8-bit memory manipulation instruction. This register does not be used in the 3-wire serial
I/O mode.
The master device outputs a slave address for selection of a particular slave device to the connected slave device.
These two data (the slave address output from the master device and the SVA value) are compared with an
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address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of serial operating
mode register 0 (CSIM0) becomes 1.
Address comparison can also be executed on the data of LSB-masked high-order 7 bits when bit 4 (SVAM) of
the interrupt timing specification register (SINT) is 1.
If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC)
is cleared to 0. In the SBI mode or the I
can be used. In this case, the interrupt request signal (INTCSI0) is generated only if the slave address output
from the master device matches the SVA value. With this interrupt request, the slave device acknowledges that
a communication request is sent from the master device. When bit 5 (SIC) of the interrupt timing specification
register (SINT) has been set to 1, the wake-up function is not available even if WUP IS 1.
(The interrupt request signal is generated at the bus release in the SBI mode, and at the stop condition in the
2
I
C mode. The SIC must be cleared to 0 while in use of the wake-up function.
Further, when SVA transmits data as the master or slave device in the SBI mode, 2-wire serial I/O mode, or I
bus mode, SVA can be used to detect errors.
RESET input makes SVA undefined.
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
2
In the I
C bus mode, do not write data to SIO0 during WUP (bit 5 of serial operation mode register
0 (CSIM0)) = 1. When wake-up function is used, data reception is available without writing data
to SIO0. For details about wake-up function, refer to 16.4.5 (1) (c) "Wake-up function".
2
C bus mode bus configurations enable the pin to serve for both
2
C bus mode, when bit 5 (WUP) of CSIM0 is 1, the wake-up function
2
C
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