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(3) Various signals
Figure 16-35 shows RELT and CMDT operations.
SO0 Latch
(4) Transfer start
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
• Serial interface channel 0 operation control bit (CSIE0) = 1
• Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Cautions 1. If CSIE0 is set to "1" after data write to SIO0, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is
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set.
(5) Error detection
In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination
device, that is, serial I/O shift register 0 (SIO0). Thus, transmit error can be detected in the following way.
(a) Method of comparing SIO0 data before transmission to that after transmission
(b) Method of using the slave address register (SVA)
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
Figure 16-35. RELT and CMDT Operations
RELT
CMDT
2. Because the N-ch open-drain output must be set to high-impedance for data reception, write
FFH to SIO0 in advance.
In this case, if two data differ from each other, a transmit error is judged to have occurred.
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, the COI
bit (match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is
tested. If it is "1", normal transmission is judged to have been carried out. If it is "0", a transmit error is judged
to have occurred.
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