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Note
This operation corresponds to the timing chart if it meets the specifications described in 16.4.7 (2) Avoidance.
Refer to 16.4.7 (2) Limitation when used as the slave device in the I
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
Figure 16-45. Data Transmission from Master to Slave
(Both Master and Slave Selected 9-Clock Wait) (3/3)
Master device operation
SIO0 ← Address
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
"H"
"L"
WUP
"L"
ACKE
CMDT
RELT
CLC
"L"
WREL
"L"
SIC
INTCSI0
Transfer line
SCL
1
2
SDA0 (SDA1)
D7
D6
Note
Slave device operation
SIO0 ← FFH
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
ACKE
"H"
"L"
CMDT
"L"
RELT
"L"
CLC
WREL
"L"
SIC
INTCSI0
(c) Stop Condition
3
4
5
6
7
8
9
D5 D4 D3 D2 D1 D0 ACK
SIO0 ← Address
1
2
3
4
A6
A5
A4
2
C bus mode, for details.
395
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