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(1) Interrupt request flag registers (IF0L, IF0H)
The interrupt request flag is set to (1) when the corresponding interrupt request is generated or an instruction
is executed. It is cleared to (0) when an instruction is executed upon acknowledgment of an interrupt request
or upon application of RESET input.
IF0L and IF0H are set with a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are used together
as a 16-bit register IF0, they are set with a 16-bit memory manipulation instruction.
RESET input sets these registers to 00H.
Symbol
<7>
IF0L
TMIF3 CSIIF1 CSIIF0
7
IF0H
0
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Note
WTIF flag is a test input flag. Vectored interrupt request is not generated.
Cautions 1. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer. If a watchdog
timer mode 1 is used, set TMIF4 flag to 0.
2. Be sure to set bits 4, 6, and 7 of IF0H to 0.
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CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION
Figure 18-2. Interrupt Request Flag Register Format
<6>
<5>
<4>
<3>
PIF3
PIF2
6
<5>
4
<3>
0
WTIF
Note
0
ADIF
<2>
<1>
<0>
Address
PIF1
PIF0
TMIF4
FFE0H
<2>
<1>
<0>
TMIF2 TMIF1 TMIF0
FFE1H
××IF
0
1
When Reset
R/W
00H
R/W
00H
R/W
Interrupt Request Flag
No interrupt request signal is generated
Interrupt request signal is generated and
interrupt requested
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