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11.4.2 Interval timer operation
The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at intervals of a
preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0.
The count clock (or interval time) can be selected with bits 0 to 2 (TCL20 to TCL22) of the time clock select register
(TCL2). When 1 is written into WDTM bit 7 (RUN), the interval timer operation starts.
When the watchdog timer operated as interval timer, the interrupt mask flag (TMMK4) and priority specify flag
(TMPR4) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interrupt
requests, the INTWDT default has the highest priority.
The interval timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set WDTM bit 7
(RUN) to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval
2. The interval time just after setting with WDTM may be shorter than the set time by up to 0.5%.
3. When the subsystem clock is selected for CPU clock, watchdog timer count operation is
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238
CHAPTER 11 WATCHDOG TIMER
timer mode is not set unless RESET input is applied.
stopped.
Table 11-5. Interval Timer Interval Time
TCL22
TCL21
TCL20
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Remark
f
: Main system clock oscillation frequency
X
TCL20 to TCL22: Bits 0 to 2 of the timer clock select register 2 (TCL2)
Interval Time
× 1/f
409.6 µ s
12
2
X
× 1/f
819.2 µ s
2
13
X
× 1/f
2
14
1.64 ms
X
× 1/f
15
2
3.28 ms
X
× 1/f
2
16
6.55 ms
X
× 1/f
17
2
13.1 ms
× 1/f
18
2
26.2 ms
X
× 1/f
2
20
104.9 ms
X
f
= 10.0 MHz
X
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