NEC 78014Y Series User Manual page 440

8-bit single-chip microcontrollers
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Figure 17-18. Operation Timings when Using Busy Control Option (BUSY0 = 0)
SCK1
SO1
SI1
BUSY
CSIIF1
TRF
Caution When TRF is cleared, the SO1 pin becomes low.
Remark CSIIF1 : Interrupt request flag
When the busy signal becomes inactive, waiting is released. If the sampled busy signal is inactive,
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transmission/reception of the next 8-bit data is started at the falling edge of the next clock.
Because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal,
even if made inactive by the slave, is sampled. It takes 0.5 clock until data transfer is started after the busy
signal was sampled.
To accurately release waiting, the slave must keep the busy signal inactive at least for the duration of 1.5
clock.
Figure 17-19 shows the timing of the busy signal and releasing the waiting. This figure shows an example
where the busy signal is active as soon as transmission/reception has been started.
SCK1
SO1
BUSY
(active high)
440
CHAPTER 17 SERIAL INTERFACE CHANNEL 1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
TRF
: Bit 3 of the automatic data transmit/receive control register (ADTC)
Figure 17-19. Busy Signal and Wait Release (when BUSY0 = 0)
D7
D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
If made inactive
immediately after
sampled
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Wait
Busy Input Clear
Busy Input Valid
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1.5 clock (min.)
Wait
Busy input released
Busy input valid

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