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(3) Various signals
Figure 15-9 shows RELT and CMDT operations.
SO0 Latch
RELT
CMDT
(4) MSB/LSB switching as the start bit
The 3-wire serial I/O mode enables to select transfer to start at MSB or LSB.
Figure 15-10 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the
figure, MSB/LSB can be read/written in inverted form.
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register
0 (CSIM0).
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Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains
unchanged.
Thus, switch the MSB/LSB start bit before writing data to the shift register.
282
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries)
Figure 15-9. RELT and CMDT Operations
Figure 15-10. Circuit of Switching in Transfer Bit Order
7
6
Internal Bus
1
0
LSB Start
Read/Write Gate
MSB Start
SI0
Shift Register 0 (SIO0)
SO0
SCK0
Read/Write Gate
SO0 Latch
D
Q
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