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7.4.3 Divider
The divider divides the main system clock oscillator output (f
7.4.4 When no subsystem clocks are used
If it is not necessary to use subsystem clocks for low power consumption operations and watch operations, connect
the XT1 and XT2 pins as follows.
XT1: Connect to V
XT2: Open
In this state, however, some current may leak via the on-chip feedback resistor of the subsystem clock oscillator
when the main system clock stops. To prevent that from happening, the above on-chip feedback resistor (PCC) can
be removed with bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and
XT2 pins as described above.
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CHAPTER 7 CLOCK GENERATOR
or V
DD
SS
) and generates various clocks.
X
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