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Avoidance:
Transfer line
SDA0 (SDA1)
Slave device operation
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
If the stop condition output timing for the µ PD78014Y Subseries device has been determined
previously (i.e. amount of communication data between the µ PD78014Y Subseries device
and the master device is fixed), then it is possible to avoid this restriction by software.
Set bit 5 (WUP) of serial operating mode register 0 (CSIM0) and serial I/O shift register 0
(SIO0) of the slave device to 1 and FFH respectively before a stop condition signal is output.
Then the wake-up function is enabled for the next slave address field which is sent from the
master device, and the N-ch open-drain output is high-impedance state automatically. As
a result, there is no influence on slave reception data.
SCL
Software
operation
SIO0
Stop condition
Start condition
WUP ← 1
SIO0 ← FFH
FEH
µ
The PD78014Y subseries
device does not influence
this bit
405
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