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(1) Serial I/O shift register 0 (SIO0)
This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift
operation) in synchronization with the serial clock.
SIO0 is set with an 8-bit memory manipulation instruction.
When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.
In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1).
In reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0.
The SBI mode and 2-wire serial I/O mode bus configurations enables the pin to serve for both input and output.
Thus, in the case of a device for reception, write FFH to SIO0 in advance (except when address reception is carried
out by setting bit 5 (WUP) of CSIM0 to 1).
In the SBI mode, the busy state can be cleared by writing data to SIO0. In this case, bit 7 (BSYE) of the serial
bus interface control register (SBIC) is not cleared to 0.
RESET input makes SIO0 undefined.
(2) Slave address register (SVA)
This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus.
SVA is set with an 8-bit memory manipulation instruction. This register does not be used in the 3-wire serial I/O
mode.
The master device outputs a slave address for selection of a particular slave device to the connected slave device.
These two data (the slave address output from the master device and the SVA value) are compared with an
address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of serial operating
mode register 0 (CSIM0) becomes 1.
Address comparison can also be executed on the data of LSB-masked high-order 7 bits when bit 4 (SVAM) of
the interrupt timing specify register (SINT) is 1.
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If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC)
is cleared to 0.
In the SBI mode, when bit 5 (WUP) of CSIM0 is 1, the wake-up function is available. In this case, the interrupt
request signal (INTCSI0) is generated only if the the slave address output from the master device matches the
value of SVA. With this interrupt request, the slave device acknowledges that a communication request is sent
from the master device. When bit 5 (SIC) of the interrupt timing specification register has been set to 1, the wake-
up function is not available even if WUP is 1. (The interrupt request signal is generated at the bus release in
the SBI mode) The SIC must be cleared to 0 while in use of the wake-up function.
Further, when SVA transmits data as the master or slave device in the SBI mode or 2-wire serial I/O mode, SVA
can be used to detect errors.
RESET input makes SVA undefined.
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries)
269
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