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Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set
number of data bytes in SCFRDR2, and no further data has arrived for at least 15 etu after the stop
bit of the last data received.
Bit 0: DR
0
1
Note: * Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format.
etu: Elementary time unit (time for transfer of 1 bit)
16.2.8
Bit Rate Register (SCBRR2)
Bit:
7
Initial value:
1
R/W:
R/W
SCBRR2 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SCSMR2.
SCBRR2 can be read or written to by the CPU at all times.
SCBRR2 is initialized to H'FF by a power-on reset or manual reset. It is not initialized in standby
mode or in the module standby state.
Rev. 3.0, 04/02, page 650 of 1064
Description
Reception is in progress or has ended normally and there is no receive data
left in SCFRDR2
[Clearing conditions]
Power-on reset or manual reset
When all the receive data in SCFRDR2 has been read after reading DR
= 1, and 0 is written to DR
When all the receive data in SCFRDR2 has been read by the DMAC
No further receive data has arrived
[Setting condition]
When SCFRDR2 contains fewer than the receive trigger set number of
receive data bytes, and no further data has arrived for at least 15 etu after
the stop bit of the last data received*
6
5
1
1
R/W
R/W
4
3
1
1
R/W
R/W
R/W
(Initial value)
2
1
1
1
R/W
R/W
0
1
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