Standby
Power-On Reset
Oscillation stops
Reset
CKIO
1
*
Normal
Standby
2
Reset
Normal
*
STATUS
0–30 Bcyc
0–10 Bcyc
Notes: *1 When standby mode is exited by means of a power-on reset, a WDT count is not
performed. Hold
low for the PLL oscillation stabilization time.
*2 Undefined
Figure 9.4 STATUS Output in Standby
Power-On Reset Sequence
Rev. 3.0, 04/02, page 232 of 1064