Hitachi SH7751 Hardware Manual page 377

When DRAM or Synchronous DRAM Interface is Set*
Note: * External wait input is always ignored
Bit 15: A3W2 Bit 14: A3W1
0 0
1
1 0
1
Note: * Inhibited in RAS down mode
Bits 11 to 9—Area 2 Wait Control (A2W2–A2W0): These bits specify the number of wait states
to be inserted for area 2. External wait input is only enabled when the SRAM interface or MPX
interface is used, and is ignored when synchronous DRAM is used. For the case where an MPX
interface setting is made, see table 13.7.


When SRAM Interface is Set
Bit 11: A2W2 Bit 10: A2W1
0 0
1
1 0
1
Rev. 3.0, 04/02, page 338 of 1064
DRAM
Bit 13: A3W0 Assertion Width
0 1
1 2
0 3
1 4
0 7
1 10
0 13
1 16
Bit 9: A2W0 Inserted Wait States
0 0
1 1
0 2
1 3
0 6
1 9
0 12
1 15 (Initial value)
Description
   
Synchronous DRAM
 
 
Inhibited
1*
2
3
4*
5*
Inhibited
Inhibited
Description
 
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Latency Cycles
Pin