Break Data Mask Register B (Bdmrb) - Hitachi SH7751 Hardware Manual

Bits 31 to 0—Break Data B31 to B0 (BDB31–BDB0): These bits hold the data (bits 31–0) to be
used in the channel B break conditions.

20.2.10 Break Data Mask Register B (BDMRB)

Bit: 31
BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24
Initial value: *
R/W: R/W
Bit: 23
BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16
Initial value:
*
R/W: R/W
Bit: 15
BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9
Initial value:
*
R/W: R/W
Bit: 7
BDMB7
Initial value:
*
R/W: R/W
Note: *: Undefined
Break data mask register B (BDMRB) is a 32-bit readable/writable register that specifies which
bits of the break data set in BDRB are to be masked. BDMRB is not initialized by a power-on
reset or manual reset.
Rev. 3.0, 04/02, page 760 of 1064
30 29
* *
R/W R/W
22 21
* *
R/W R/W
14 13
* *
R/W R/W
6 5
BDMB6 BDMB5 BDMB4
* *
R/W R/W
28 27
* *
R/W R/W R/W
20 19
* *
R/W R/W R/W
12 11
* *
R/W R/W R/W
4 3
BDMB3 BDMB2
* *
R/W R/W R/W
26 25 24
* *
R/W R/W
18 17 16
* *
R/W R/W
10 9
BDMB8
* *
R/W R/W
2 1
BDMB1 BDMB0
* *
R/W R/W
*
*
8
*
0
*