Figure 22.7 Master Write Cycle In Host Mode (Single) - Hitachi SH7751 Hardware Manual

PCICLK
AD31–AD0
PAR
C/ –C/
IDSEL
/ ,
–
/ ,
–

Figure 22.7 Master Write Cycle in Host Mode (Single)

Addr
Com
Addr: PCI space address
Dn: nth data
AP: Address parity
DPn: nth data parity
Com: Command
BEn: nth data byte enable
D0
AP DP0
BE0
LOCKed
Rev. 3.0, 04/02, page 899 of 1064