Register Descriptions; Receive Shift Register (Scrsr2); Receive Fifo Data Register (Scfrdr2) - Hitachi SH7751 Hardware Manual

16.2

Register Descriptions

16.2.1

Receive Shift Register (SCRSR2)

Bit: 7
R/W: —
SCRSR2 is the register used to receive serial data.
The SCIF sets serial data input from the RxD2 pin in SCRSR2 in the order received, starting with
the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to the receive FIFO register, SCFRDR2, automatically.
SCRSR2 cannot be directly read or written to by the CPU.
16.2.2

Receive FIFO Data Register (SCFRDR2)

Bit: 7
R/W: R
SCFRDR2 is a 16-stage FIFO register that stores received serial data.
When the SCIF has received one byte of serial data, it transfers the received data from SCRSR2 to
SCFRDR2 where it is stored, and completes the receive operation. SCRSR2 is then enabled for
reception, and consecutive receive operations can be performed until the receive FIFO register is
full (16 data bytes).
SCFRDR2 is a read-only register, and cannot be written to by the CPU.
If a read is performed when there is no receive data in the receive FIFO register, an undefined
value will be returned. When the receive FIFO register is full of receive data, subsequent serial
data is lost.
The contents of SCFRDR2 are undefined after a power-on reset or manual reset.
6 5
— — —
6 5
R R
4 3
— —
4 3
R R R
Rev. 3.0, 04/02, page 637 of 1064
2 1 0
— —
2 1 0
R R