Hitachi SH7751 Hardware Manual page 378

When Synchronous DRAM Interface is Set *
Bit 11: A2W2 Bit 10: A2W1
0 0
1
1 0
1
Notes: *1 External wait input is always ignored
*2 Inhibited in RAS down mode
Bits 8 to 6—Area 1 Wait Control (A1W2–A1W0): These bits specify the number of wait states
to be inserted for area 1. For the case where an MPX interface setting is made, see table 13.7.
Bit 8: A1W2 Bit 7: A1W1
0 0
1
1 0
1
1
Description
Bit 9: A2W0 Synchronous DRAM
0 Inhibited
2
1 1*
0 2
1 3
2
0 4*
2
1 5*
0 Inhibited
1 Inhibited
Bit 6: A1W0 Inserted Wait States
0 0
1 1
0 2
1 3
0 6
1 9
0 12
1 15 (Initial value)
   
Latency Cycles
Description
 
Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Rev. 3.0, 04/02, page 339 of 1064