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Appendix G Power-On and Power-Off Procedures
Power-on
Supply the internal power after supplying power to the I/O, RTC, and CPG. *
Supply power to V
At power-on, the
before (or at the same time as) entering the signal lines (
MD10, and external clock). If the signal lines are entered first, the LSI may be damaged.
Input high level to
power supply voltage.
Power-off
When turning off the power, there are no restrictions for the timing of
Turn off the I/O, RTC, CPG power supply voltage after (or at the same time as) * turning
off the internal power supply voltage.
Note however that the internal power supply voltage may exceed the I/O, RTC, CPG power
supply voltage by a maximum of 0.3 V only when the system is being turned off.
The power supply level must be lowered in compliance with the I/O, RTC, CPG power
supply voltage.
Note: * 10 ms or less for the HD6417751R.
The ratings and procedures for power-on and power-off are given below.
V
= V
DDQ
DD-RTC
The LSI may be damaged if
0.3 V < V
in
0.3 V < V
DD
are not satisfied when V
2.0 V
1.2 V
GND
0 ≤ t
Note: * HD6417751R only
Rev. 3.0, 04/02, page 1062 of 1064
, V
, and V
DDQ
DD-RTC
signal is low. Normally, supply power to the I/O, RTC, and CPG
in compliance with the voltage level of the I/O, RTC, CPG
= V
= 0 V
DD-CPG
< V
+ 0.3 V
DDQ
, V
< V
+ 0.3 V
DD-PLL1/2
DDQ
= V
= V
DDQ
DD-RTC
Power-on
t
on
< 10 ms*
on
Figure G.1 Power-On and Power-Off Procedures
simultaneously.
DD-CPG
.
DD-CPG
V
DDQ
V
, V
DD
DD-PLL1/2
,
, MD0 to
,
Power-off
t
off
0 ≤ t
< 10 ms*
off
.
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