Cpg Register Description; Frequency Control Register (Frqcr) - Hitachi SH7751 Hardware Manual

10.4

CPG Register Description

10.4.1

Frequency Control Register (FRQCR)

The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies
use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU
clock, bus clock, and peripheral module clock frequency division ratios. Only word access can be
used on FRQCR.
FRQCR is initialized only by a power-on reset via the
determined by the clock operating mode.
Bit: 15
—
Initial value: 0
R/W: R/W
Bit: 7
IFC1
Initial value: —
R/W: R/W
Bits 15 to 12—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 11—Clock Output Enable (CKOEN): Specifies whether a clock is output from the CKIO
pin or the CKIO pin is placed in the high-impedance state. When the CKIO pin goes to the high-
impedance state, operation continues at the operating frequency before this state was entered.
When the CKIO pin becomes high-impedance, it is pulled up.
Bit 11: CKOEN
0
1
Note: * It is not pulled up in hardware standby mode.
Bit 10—PLL Circuit 1 Enable (PLL1EN): Specifies whether PLL circuit 1 is on or off.
Bit 10: PLL1EN
0
1
14 13
— —
0 0
R/W R/W
6 5
IFC0 BFC2
— —
R/W R/W
Description
CKIO pin goes to high-impedance state (pulled up*)
Clock is output from CKIO pin
Description
PLL circuit 1 is not used
PLL circuit 1 is used


pin. The initial value of each bit is
12 11
— CKOEN PLL1EN PLL2EN
0 1
R R/W
4 3
BFC1 BFC0
— —
R/W R/W
Rev. 3.0, 04/02, page 249 of 1064
10 9
1 1
R/W R/W
2 1
PFC2 PFC1 PFC0
— —
R/W R/W
(Initial value)
(Initial value)
8
IFC2
—
R/W
0
—
R/W