Memory Control Register (Mcr) - Hitachi SH7751 Hardware Manual

13.2.8

Memory Control Register (MCR)

The memory control register (MCR) is a 32-bit readable/writable register that specifies
 
timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address
multiplexing, and refresh control. This enables DRAM and synchronous DRAM to be connected
without using external circuitry.
MCR is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. Bits RASD, MRSET, TRC2–0, TPC2–0, RCD1–0, TRWL2–0, TRAS2–0, BE,
SZ1–0, AMXEXT, AMX2–0, and EDOMODE are written in the initialization following a power-
on reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the
same values should be written to the other bits so that they remain unchanged. When using DRAM
or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is
completed.
Bit: 31
RASD
Initial value: 0
R/W: R/W
Bit: 23
TCAS
Initial value: 0
R/W: R/W
Bit: 15
TRWL2
Initial value: 0
R/W: R/W
Bit: 7
SZ0
Initial value: 0
R/W: R/W
Rev. 3.0, 04/02, page 344 of 1064
30 29
MRSET TRC2
0 0
R/W R/W
22 21
— TPC2
0 0
R R/W
14 13
TRWL1 TRWL0
0 0
R/W R/W
6 5
AMXEXT AMX2
0 0
R/W R/W
28 27
TRC1 TRC0
0 0
R/W R/W
20 19
TPC1 TPC0
0 0
R/W R/W
12 11
TRAS2 TRAS1
0 0
R/W R/W
4 3
AMX1 AMX0
0 0
R/W R/W


26 25
— —
0 0
R R
18 17
— RCD1
0 0
R R/W
10 9
TRAS0 BE
0 0
R/W R/W
2 1
RFSH RMODE
0 0
R/W R/W
and
24
—
0
R
16
RCD0
0
R/W
8
SZ1
0
R/W
0
EDO
MODE
0
R/W