Hitachi SH7751 Hardware Manual page 374

Bits 31 to 29—Area 6 Wait Control (A6W2–A6W0): These bits specify the number of wait
states to be inserted for area 6. For the case where an MPX interface setting is made, see table
13.7.
Bit 31: A6W2 Bit 30: A6W1
0 0
1
1 0
1
Bits 28 to 26—Area 6 Burst Pitch (A6B2–A6B0): These bits specify the number of wait states to
be inserted from the second data access onward at the time of setting the burst ROM in a burst
transfer.
Bit 28: A6B2 Bit 27: A6B1
0 0
1
1 0
1
Bit 29: A6W0 Inserted Wait States
0 0
1 1
0 2
1 3
0 6
1 9
0 12
1 15 (Initial value)
Wait States Inserted
from Second Data
Bit 26: A6B0 Access Onward
0 0
1 1
0 2
1 3
0 4
1 5
0 6
1 7 (Initial value)
Description
First Cycle
Description
Burst Cycle (Excluding First Cycle)
Rev. 3.0, 04/02, page 335 of 1064
 
Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled


Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled