Hitachi SH7751 Hardware Manual page 854

Bit 21: 66M
0
1
Bit 20—PCI Power Management (PM): Shows whether the PCI power management is
supported.
Bit 20: PM
0
1
Bits 19 to 10—Reserved: These bits always return 0 when read. Always write 0 to these bits.
Bit 9—High-Speed Back-To-Back Control (PBBE): Selects whether or not to allow high-speed
back-to-back control with different targets when privileged as the master.
Bit 9: PBBE
0
1
     
Output Control (SER): Controls the
Bit 8—
Bit 8: SER
0
1
Bit 7—Wait Cycle Control (WCC): Controls the address/data stepping. When WCC=1, address
and data are output in master write operations, only address is output in master read operations,
and only data is output in target read operations, at least in two clocks.
Bit 7: WCC
0
1
Bit 6—Parity Error Response (PER): Controls the device response when a parity error is
detected or a parity error report is received.
Description
This device supports 33 MHz operation
This device supports 66 MHz operation
Description
Power management not supported
Power management supported
Description
Allows high-speed back-to-back control only with same target (Initial value)
Allows high-speed back-to-back control with different target (Not supported)
Description



output disabled (Hi-Z)



output enabled
Description
Disable address/data stepping control
Enable address/data stepping control

output.

is asserted only when PER = 1.
Rev. 3.0, 04/02, page 815 of 1064
(Initial value)
(Initial value)
(Initial value)
(Initial value)