Figure 23.34(A) Synchronous Dram Bus Cycle: Mode Register Setting (Pall) - Hitachi SH7751 Hardware Manual

TRp1 TRp2
CKIO
t
AD
Bank
Precharge-sel
Address
t
CSD
t
RWD
RD/
t
RASD
t
CASD2
t
DQMD
DQMn
t
WDD
D31–D0
(write)
CKE
t
DACD
DACKn
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high

Figure 23.34(a) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL)

TRp3 TRp4
t
CSD
t
CASD2
TMw TMw2 TMw3
t
AD
t
RWD
t
RASD
t
CASD2
Rev. 3.0, 04/02, page 989 of 1064
TMw4 TMw5
t
AD
t
CSD
t
RWD
t
RASD
t
CASD2
t
DQMD
t
WDD
t
BSD
t
DACD