Hitachi SH7751 Hardware Manual page 593

Table 14.14 Register Configuration (cont)
Chan-
nel Name
4 DMA source
address register 4
DMA destination
address register 4
DMA transfer
count register 4
DMA channel
control register 4
5 DMA source
address register 5
DMA destination
address register 5
DMA transfer
count register 5
DMA channel
control register 5
6 DMA source
address register 6
DMA destination
address register 6
DMA transfer
count register 6
DMA channel
control register 6
7 DMA source
address register 7
DMA destination
address register 7
DMA transfer
count register 7
DMA channel
control register 7
Notes: Longword access should be used for all control registers. If a different access width is
used, reads will return all 0s and writes will not be possible.
* Bit 1 of CHCR0–CHCR3 and bits 2 and 1 of DMAOR can only be written with 0 after
being read as 1, to clear the flags.
Rev. 3.0, 04/02, page 554 of 1064
Abbre- Read/
viation Write
SAR4 R/W
DAR4 R/W
DMATCR4 R/W
CHCR4 R/W*
SAR5 R/W
DAR5 R/W
DMATCR5 R/W
CHCR5 R/W*
SAR6 R/W
DAR6 R/W
DMATCR6 R/W
CHCR6 R/W*
SAR7 R/W
DAR7 R/W
DMATCR7 R/W
CHCR7 R/W*
Initial Value P4 Address
Undefined H'FFA00050 H'1FA00050 32
Undefined H'FFA00054 H'1FA00054 32
Undefined H'FFA00058 H'1FA00058 32
H'00000000 H'FFA0005C H'1FA0005C 32
Undefined H'FFA00060 H'1FA00060 32
Undefined H'FFA00064 H'1FA00064 32
Undefined H'FFA00068 H'1FA00068 32
H'00000000 H'FFA0006C H'1FA0006C 32
Undefined H'FFA00070 H'1FA00070 32
Undefined H'FFA00074 H'1FA00074 32
Undefined H'FFA00078 H'1FA00078 32
H'00000000 H'FFA0007C H'1FA0007C 32
Undefined H'FFA00080 H'1FA00080 32
Undefined H'FFA00084 H'1FA00084 32
Undefined H'FFA00088 H'1FA00088 32
H'00000000 H'FFA0008C H'1FA0008C 32
Area 7 Access
Address Size