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Bits 7 to 0—Cache Line Size (CACHE7 to 0): Not supported. Memory target is set cache-
disabled, and SDONE and
22.2.5
PCI Configuration Register 4 (PCICONF4)
Bit:
31
BASE31 BASE30 BASE29 BASE28 BASE27 BASE26 BASE25 BASE24
Initial value:
0
PCI-R/W:
R/W
PP Bus-R/W:
R/W
Bit:
23
BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16
Initial value:
0
PCI-R/W:
R/W
PP Bus-R/W:
R/W
Bit:
15
BASE15 BASE14 BASE13 BASE12 BASE11 BASE10
Initial value:
0
PCI-R/W:
R/W*
PP Bus-R/W:
R/W*
Bit:
7
BASE7
Initial value:
0
PCI-R/W:
R
PP Bus-R/W:
R
Note: * These bits are read-only in the SH7751 and can be read from and written to in the
SH7751R.
PCI configuration register 4 (PCICONF4) is a 32-bit read/partial-write register that accommodates
the I/O-space base address register, which is one of the PCI configuration registers that are
stipulated in the PCI's local-bus specifications. PCICONF4 holds the higher-order bits of the
address used when a device on the PCI bus uses I/O transfer commands to access a local register
in the PCIC.
are ignored.
30
29
0
0
R/W
R/W
R/W
R/W
22
21
0
0
R/W
R/W
R/W
R/W
14
13
0
0
R/W*
R/W*
R/W*
R/W*
6
5
BASE6
BASE5
0
0
R
R
R
R
28
27
0
0
R/W
R/W
R/W
R/W
20
19
0
0
R/W
R/W*
R/W
R/W*
12
11
0
0
R/W*
R/W*
R/W*
R/W*
4
3
BASE4
BASE3
BASE2
0
0
R
R
R
R
Rev. 3.0, 04/02, page 821 of 1064
26
25
0
0
R/W
R/W
R/W
R/W
18
17
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
10
9
BASE9
BASE8
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
2
1
—
0
0
R
R
R
R
24
0
R/W
R/W
16
0
8
0
0
ASI
1
R
R
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