Dma Transfer Count Registers 0-7 (Dmatcr0-Dmatcr7); Dma Channel Control Registers 0-7 (Chcr0-Chcr7) - Hitachi SH7751 Hardware Manual

14.7.3 DMA Transfer Count Registers 0 – 7 (DMATCR0 – DMATCR7)
Bit: 31 30
Initial value: 0 0
R/W: R R
Bit: 15 14
Initial value: — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMA transfer count registers 0–7 (DMATCR0–DMATCR7) are 32-bit readable/writable registers
that specify the number of transfers in transfer operations for the corresponding channel
(bytecount, word count, longword count, quadword count, or 32-byte count). Functions of these
registers are the same as the transfer-count registers of the SH7751. For more information, see
section 14.2.3, DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3).
14.7.4 DMA Channel Control Registers 0 – 7 (CHCR0 – CHCR7)
Bit: 31 30
SSA2 SSA1 SSA0 STC DSA2 DSA1 DSA0 DTC
Initial value: 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
Initial value: 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (R/W) R/W (R/W) R/W
DMA channel control registers 0–7(CHCR0–CHCR7) are 32-bit readable/writable registers that
specify the operating mode, transfer method, etc., for each channel. Bits 31–28 and 27–24
correspond to the source address and destination address, respectively; these settings are only
valid when the transfer involves the CS5 or CS6 space and the relevant space has been specified as
a PCMCIA-interface space. In other cases, these bits should be cleared to 0. For more information
about the PCMCIA interface, see section 13.3.7, PCMCIA Interface.
No function is assigned to bits 18 and 16 of the CHCR2–CHCR7 registers. Writing to these bits of
the CHCR2–CHCR7 registers is invalid. If, however, a value is written to these bits, it should
always be 0. These bits are always read as 0.
Rev. 3.0, 04/02, page 556 of 1064
29 28 27 26
0 0 0 0
R R R R
13 12 11 10
— — — —
29 28 27 26
0 0 0 0
13 12 11 10
0 0 0 0
25 24 23 22
0 0 — —
R R R/W R/W R/W R/W R/W R/W R/W R/W
9 8 7 6
— — — —
25 24 23 22
— —
0 0 0 0
R R
9 8 7 6
TM TS2 TS1 TS0 QCL
0 0 0 0
21 20 19 18
— — — —
5 4 3 2
— — — —
21 20 19 18
— — DS RL
0 0 0 0
R R R/W (R/W) R/W (R/W)
5 4 3 2
IE
0 0 0 0
17 16
— —
1 0
— —
17 16
AM AL
0 0
1 0
TE DE
0 0