Block Diagram (Sh7751); Figure 14.1 Block Diagram Of Dmac - Hitachi SH7751 Hardware Manual

14.1.2

Block Diagram (SH7751)

Figure 14.1 shows a block diagram of the DMAC.
On-chip
peripheral
module
TMU
SCI, SCIF
DACK0, DACK1
DRAK0, DRAK1
,
External bus
D[31:0]
ID[1:0]
DMAOR: DMAC operation register
SARn: DMAC source address
register
DARn: DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
(n: 0 to 3)
Rev. 3.0, 04/02, page 466 of 1064
interface
32B data
buffer
DBREQ
Bus state DDTMODE
controller
BAVL
DDTD
id[1:0]
tdack

Figure 14.1 Block Diagram of DMAC

DMAC module
Count
control
Register
control
DMATCRn
Activation
control
Request
priority
control
Bus
4
dreq0-3
DDT module
DTR command buffer
CH0 CH1
Request controller
48 bits
SARn
DARn
CHCRn
DMAOR
SAR0, DAR0, DMATCR0,
CHCR0 only
CH2 CH3